As CMOS technology continued to scale, metal gate electrodes were introduced to overcome the deleterious effects of doped polysilicon, namely gate electrode depletion, high resistance, and incompatibility with high-κ gate dielectrics. Every metal has a characteristic work function, which is a key material parameter that affects device threshold voltage. A work function is the energy needed to move an electron in the solid atom from the Fermi level to the valance band. Ideally, the Fermi energy value of a metal gate in NMOS area exists near a conduction band of silicon, while that of the other metal gate in the PMOS area exists near a valance band of silicon. Therefore, dual-metal gates using different metals may be conventionally used for NMOS and PMOS transistors. A method of forming dual-metal gates in a semiconductor device according to the prior art is explained by referring to FIG. 1a to FIG. 1d as follows.
FIGS. 1a to 1d illustrate cross-sectional views of the process of forming gates in a semiconductor device according to the prior art. Referring to FIG. 1a, a semiconductor substrate 10, having an STI region 12 is provided. An N well and a P well (not shown in the drawings) are formed respectively in the semiconductor substrate 10 using masking and ion implantation processes known in the art. A high-κ gate dielectric 14 is deposited. A P-metal layer 16 is disposed on the high-κ dielectric. The P-metal layer 16 is formed of a metal material of which the Fermi energy lies near a valance band of silicon. Referring to FIG. 1b, the P-metal 16 at NMOS area 18 is etched away. The high-κ gate dielectric 14 may be damaged. As illustrated in FIG. 1c, the N-metal 20 is then deposited. The N-metal 20 is a metal material of which the Fermi energy lies near a conduction band of silicon. In FIG. 1d, the N-metal 20 at the PMOS area is shown etched away. Thus, a conventional dual metal gate structure is fabricated.
One disadvantage of the prior art is that the conventional dual metal gate process uses two separate metals for NMOS and PMOS. The metal etching process uses the gate dielectric as a stop layer, potentially damaging the gate dielectric. Further, the dual metal gate process is complex and is therefore expensive to manufacture.
Another method of processing is a phase-controlled FUSI gate process. The phase-controlled FUSI gate process uses different silicide phases to control the effective work function of the PMOS and NMOS transistors. Different silicide phases of Ni include NiSi, Ni2Si, Ni3Si, etc. A suitable threshold voltage may be realized for both PMOS and NMOS based on the composition control of Hf in the dielectric film and Ni in the electrode. NiSi and Ni3Si electrodes may be formed on a HfO2 composition for NMOS and PMOS. A description of a process for forming a phase-controlled FUSI gate in a semiconductor device according to the prior art is explained by referring to FIG. 2a to FIG. 2q as follows.
Referring to FIG. 2a, a semiconductor substrate 20, having an isolation dielectric between an N-well and a P-well structure (not shown) is provided. A high-κ gate dielectric 22 is deposited, and a poly-Si gate stack 24 comprising poly/oxide/poly layers is then disposed. A hard mask 26 is deposited for gate patterning. FIG. 2b shows substrate 20 following a gate etch step. FIG. 2c illustrates a series of process steps, including a dummy spacer 28 deposition (dummy spacer may include an oxide film and/or a SiN film), a PMOS photolithography, and a spacer/recess etch 30. FIG. 2d shows the result of a SiGe deposition 32. In FIG. 2e, the dummy spacer is removed. FIG. 2f is a view of substrate 20 after a pocket LDD implant 34 has been performed, and a SiN offset spacer 36 has been formed. FIG. 2g shows a cross-sectional view of the substrate following spacer 38 formation (main spacer may include an oxide film and/or a SiN film), source/drain 40 implants, anneals, and an RPO 42 (such as silicon oxide). FIG. 2h shows RPO removal and nickel metal deposition 44 for the silicidation process on the source/drain regions 40. FIG. 2i shows the source/drain regions 40 after silicidation. FIG. 2j shows capping oxide/SiN dep 46 (capping layer may include an oxide film and/or a SN film). FIG. 2k shows PR coating 48. FIG. 21 shows the gate stack 24 following a series of etch back processes to expose the top of the gate stack 24. FIG. 2m shows capping SiN 46 removal, and FIG. 2n shows capping oxide/hard mask 26 removal. FIG. 2o shows PR 48 strip. Next, the polysilicon gate stack 24 is etched back in the PMOS area 50 only (using photoresist to block NMOS area, not shown) in FIG. 2p. Therefore, the polysilicon gate stack 24 in the PMOS area is thinner than the polysilicon gate stack 24 in the NMOS area. Finally, a thick Ni metal deposition and full silicidation 52 of the remaining gate poly follows, with the resultant cross sectional view shown in FIG. 2q. This configuration has a PMOS area with metal-rich silicide, such as Ni3Si, which is suited for P-FET, and an NMOS area with mono-silicide, NiSi, which is suited for an N-FET.
An unfortunate artifact of the phase-controlled FUSI gate process is that it forms different thicknesses of poly, causing height differences between the NMOS and PMOS. This process, just as the dual metal process discussed above, is also complex, and may introduce variation during the PMOS polysilicon etch back process. The process used to achieve full-gate silicidation may induce an unacceptable amount of stress in the circuitry and degrade integrity of gate dielectric.